2 research outputs found
Mixed-level identification of fault redundancy in microprocessors
A new high-level implementation independent functional fault model for
control faults in microprocessors is introduced. The fault model is based on
the instruction set, and is specified as a set of data constraints to be
satisfied by test data generation. We show that the high-level test, which
satisfies these data constraints, will be sufficient to guarantee the detection
of all non-redundant low level faults. The paper proposes a simple and fast
simulation based method of generating test data, which satisfy the constraints
prescribed by the proposed fault model, and a method of evaluating the
high-level control fault coverage for the proposed fault model and for the
given test. A method is presented for identification of the high-level
redundant faults, and it is shown that a test, which provides 100% coverage of
non-redundant high-level faults, will also guarantee 100% non-redundant SAF
coverage, whereas all gate-level SAF not covered by the test are identified as
redundant. Experimental results of test generation for the execution part of a
microprocessor support the results presented in the paper.Comment: 2019 IEEE Latin American Test Symposium (LATS